From 39f58d127f549103790cf550a58c6bf457a150d0 Mon Sep 17 00:00:00 2001 From: coolGi Date: Fri, 13 Jun 2025 23:40:47 +0930 Subject: [PATCH] added patch file --- .../bigscreen-beyond-kernel-6.15.patch | 243 ++++++++++++++++++ 1 file changed, 243 insertions(+) create mode 100644 content/docs/hardware/bigscreen-beyond-kernel-6.15.patch diff --git a/content/docs/hardware/bigscreen-beyond-kernel-6.15.patch b/content/docs/hardware/bigscreen-beyond-kernel-6.15.patch new file mode 100644 index 0000000..6875a96 --- /dev/null +++ b/content/docs/hardware/bigscreen-beyond-kernel-6.15.patch @@ -0,0 +1,243 @@ +diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c +index 3b4065099..639699e3b 100644 +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -189,6 +189,9 @@ static const struct edid_quirk { + /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ + EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), + ++ /* Bigscreen Beyond Headset */ ++ EDID_QUIRK('B', 'I', 'G', 0x1234, EDID_QUIRK_NON_DESKTOP), ++ + /* Valve Index Headset */ + EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), + EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), + +From c33583995576e9ac532c4ad9e260324b1c4fa3a3 Mon Sep 17 00:00:00 2001 +From: Yaroslav Bolyukin +Date: Sun, 30 Oct 2022 19:04:26 +0100 +Subject: [PATCH 3/3] drm/amd: use fixed dsc bits-per-pixel from edid + +VESA vendor header from DisplayID spec may contain fixed bit per pixel +rate, it should be respected by drm driver + +Signed-off-by: Yaroslav Bolyukin +Reviewed-by: Wayne Lin +--- + drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 ++ + drivers/gpu/drm/amd/display/dc/dc_types.h | 3 +++ + 2 files changed, 5 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +index 38d71b5c1f2d..f2467b64268b 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +@@ -103,6 +103,8 @@ static bool dc_stream_construct(struct dc_stream_state *stream, + + /* EDID CAP translation for HDMI 2.0 */ + stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; ++ stream->timing.dsc_fixed_bits_per_pixel_x16 = ++ dc_sink_data->edid_caps.dsc_fixed_bits_per_pixel_x16; + + memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); + stream->timing.dsc_cfg.num_slices_h = 0; +diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h +index dc78e2404b48..65915a10ab48 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_types.h +@@ -231,6 +231,9 @@ struct dc_edid_caps { + bool edid_hdmi; + bool hdr_supported; + ++ /* DisplayPort caps */ ++ uint32_t dsc_fixed_bits_per_pixel_x16; ++ + struct dc_panel_patch panel_patch; + }; + +-- +2.38.1 + + +diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c +index 3b4065099..15268afa3 100644 +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -6391,7 +6391,7 @@ static void drm_parse_vesa_mso_data(struct drm_connector *connector, + if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) + return; + +- if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { ++ if (block->num_bytes < 5) { + drm_dbg_kms(connector->dev, + "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", + connector->base.id, connector->name); +@@ -6414,24 +6414,37 @@ static void drm_parse_vesa_mso_data(struct drm_connector *connector, + break; + } + +- if (!info->mso_stream_count) { +- info->mso_pixel_overlap = 0; +- return; +- } ++ info->mso_pixel_overlap = 0; ++ ++ if (info->mso_stream_count) { ++ info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); ++ ++ if (info->mso_pixel_overlap > 8) { ++ drm_dbg_kms(connector->dev, ++ "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", ++ connector->base.id, connector->name, ++ info->mso_pixel_overlap); ++ info->mso_pixel_overlap = 8; ++ } + +- info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); +- if (info->mso_pixel_overlap > 8) { + drm_dbg_kms(connector->dev, +- "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", +- connector->base.id, connector->name, +- info->mso_pixel_overlap); +- info->mso_pixel_overlap = 8; ++ "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", ++ connector->base.id, connector->name, ++ info->mso_stream_count, info->mso_pixel_overlap); ++ } ++ ++ if (block->num_bytes < 7) { ++ /* DSC bpp is optional */ ++ return; + } + ++ info->dp_dsc_bpp = FIELD_GET(DISPLAYID_VESA_DSC_BPP_INT, vesa->dsc_bpp_int) * 16 + ++ FIELD_GET(DISPLAYID_VESA_DSC_BPP_FRACT, vesa->dsc_bpp_fract); ++ + drm_dbg_kms(connector->dev, +- "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", +- connector->base.id, connector->name, +- info->mso_stream_count, info->mso_pixel_overlap); ++ "[CONNECTOR:%d:%s] DSC bits per pixel %u\n", ++ connector->base.id, connector->name, ++ info->dp_dsc_bpp); + } + + static void drm_update_mso(struct drm_connector *connector, +@@ -6479,6 +6492,7 @@ static void drm_reset_display_info(struct drm_connector *connector) + info->mso_stream_count = 0; + info->mso_pixel_overlap = 0; + info->max_dsc_bpp = 0; ++ info->dp_dsc_bpp = 0; + + kfree(info->vics); + info->vics = NULL; +diff --git a/drivers/gpu/drm/drm_edid.c.rej b/drivers/gpu/drm/drm_edid.c.rej +new file mode 100644 +index 000000000..de3b3bf4e +--- /dev/null ++++ b/drivers/gpu/drm/drm_edid.c.rej +@@ -0,0 +1,9 @@ ++diff a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c (rejected hunks) ++@@ -6376,6 +6389,7 @@ static void drm_reset_display_info(struct drm_connector *connector) ++ info->mso_stream_count = 0; ++ info->mso_pixel_overlap = 0; ++ info->max_dsc_bpp = 0; +++ info->dp_dsc_bpp = 0; ++ } ++ ++ static u32 update_display_info(struct drm_connector *connector, +diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h +index fe88d7fc6..1de1d1726 100644 +--- a/include/drm/drm_connector.h ++++ b/include/drm/drm_connector.h +@@ -803,6 +803,12 @@ struct drm_display_info { + */ + u32 max_dsc_bpp; + ++ /** ++ * @dp_dsc_bpp: DP Display-Stream-Compression (DSC) timing's target ++ * DST bits per pixel in 6.4 fixed point format. 0 means undefined ++ */ ++ u16 dp_dsc_bpp; ++ + /** + * @vics: Array of vics_len VICs. Internal to EDID parsing. + */ +diff --git a/include/drm/drm_connector.h.rej b/include/drm/drm_connector.h.rej +new file mode 100644 +index 000000000..d54d40443 +--- /dev/null ++++ b/include/drm/drm_connector.h.rej +@@ -0,0 +1,13 @@ ++diff a/include/drm/drm_connector.h b/include/drm/drm_connector.h (rejected hunks) ++@@ -721,6 +721,11 @@ struct drm_display_info { ++ * monitor's default value is used instead. ++ */ ++ u32 max_dsc_bpp; +++ /** +++ * @dp_dsc_bpp: DP Display-Stream-Compression (DSC) timing's target +++ * DST bits per pixel in 6.4 fixed point format. 0 means undefined +++ */ +++ u16 dp_dsc_bpp; ++ }; ++ ++ int drm_display_info_set_bus_formats(struct drm_display_info *info, +diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h +index 566497eeb..3a4bd0816 100644 +--- a/drivers/gpu/drm/drm_displayid_internal.h ++++ b/drivers/gpu/drm/drm_displayid_internal.h +@@ -131,12 +131,16 @@ struct displayid_detailed_timing_block { + + #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0) + #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5) ++#define DISPLAYID_VESA_DSC_BPP_INT GENMASK(5, 0) ++#define DISPLAYID_VESA_DSC_BPP_FRACT GENMASK(3, 0) + + struct displayid_vesa_vendor_specific_block { + struct displayid_block base; + u8 oui[3]; + u8 data_structure_type; + u8 mso; ++ u8 dsc_bpp_int; ++ u8 dsc_bpp_fract; + } __packed; + + /* +diff --git a/include/drm/drm_displayid.h.rej b/include/drm/drm_displayid.h.rej +new file mode 100644 +index 000000000..61fbd38e0 +--- /dev/null ++++ b/include/drm/drm_displayid.h.rej +@@ -0,0 +1,18 @@ ++diff a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h (rejected hunks) ++@@ -131,12 +131,16 @@ struct displayid_detailed_timing_block { ++ ++ #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0) ++ #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5) +++#define DISPLAYID_VESA_DSC_BPP_INT GENMASK(5, 0) +++#define DISPLAYID_VESA_DSC_BPP_FRACT GENMASK(3, 0) ++ ++ struct displayid_vesa_vendor_specific_block { ++ struct displayid_block base; ++ u8 oui[3]; ++ u8 data_structure_type; ++ u8 mso; +++ u8 dsc_bpp_int; +++ u8 dsc_bpp_fract; ++ } __packed; ++ ++ /* DisplayID iteration */ + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +index d4395b92fb85..6c7f589e19ac 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +@@ -136,6 +136,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps( + + edid_caps->edid_hdmi = connector->display_info.is_hdmi; + ++ edid_caps->dsc_fixed_bits_per_pixel_x16 = connector->display_info.dp_dsc_bpp; ++ + apply_edid_quirks(dev, edid_buf, edid_caps); + + sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);